1. Field of the Invention
This invention relates to a semiconductor IC device having a multilayer interconnection structure and a method for manufacturing the device, and more particularly to a connecting structure between a first-level metal wiring layer and a second-level metal wiring layer and a method for forming the structure.
2. Description of the Related Art
In the case of conventional semiconductor IC devices, a first-level metal wiring layer is electrically connected to a second-level metal wiring layer as shown in FIG. 1. First, a semiconductor layer 41 consisting of an impurity diffusion layer or the like, which serves as wiring or an active region of semiconductor elements, is formed in a major surface region of a semiconductor substrate 40. Then, a first interlayer insulating film 42 is formed on the semiconductor layer 41, and a first-level metal wiring layer 43 is formed on the insulating film 42. The wiring layer 43 is obtained by forming a metal layer by sputtering and then patterning the metal layer. A second interlayer insulating film 44 is provided on the insulating film 42 and the wiring layer 43. Subsequently, a through hole 45 is formed, by photoetching process (PEP) and reactive ion etching (RIE), in that portion of the second interlayer insulating film 44 which is located on the wiring layer 43. A metal layer is formed by sputtering on an exposed portion of the wiring layer 43 and on the insulating film 44, and is then patterned to form a second-level metal wiring layer 46 electrically connected to the first-level metal wiring layer 43.
In general, as is shown in FIG. 1, the first-level metal wiring layer 43 has right and left end portions of a width .DELTA.a which are provided in consideration of mask misalignment, which may occur when a mask is aligned with the wiring layer 43 in order to form the through hole 45. Thus, the first-level metal wiring layer 43 has a width 2.DELTA.a wider than the through hole 45.
FIG. 2 shows the structure of a contact portion obtained when a mask misalignment has occurred where there is no width allowance. As is shown in FIG. 2, where no width allowance is imparted to the wiring layer 43, if a mask is misaligned from a correct position at the time of forming the through hole 45 by use of the RIE method, part of the semiconductor layer 41 and part of the interlayer insulating film 42 may be etched as well as part of the interlayer insulating film 44, thereby short-circuiting the second-level metal wiring layer 46 and the semiconductor layer 41 or the substrate 40. Further, the contact area between the first and second metal wiring layers 43 and 46 will be reduced, and accordingly the contact resistance be increased. To obtain satisfactory contact, it is necessary to provide a relatively wide width .DELTA.a at each of the right and left ends of the first-level metal wiring layer 43 in consideration of misalignment of a mask which may occur at the time of forming the through hole 45.
However, imparting the first-level metal wiring layer with a sufficient width allowance will limit high densification of layers of the same type in the case of a pattern layout as shown in FIG. 3, in which the contact portions of the layers are adjacent to one another. FIG. 3 shows an example of a pattern layout as regards the first-level metal wiring layer 43 shown in FIG. 1, in which only two adjacent metal wiring layers 43-1 and 43-2 are shown. Each of the layers 43-1 and 43-2 has a region 2.DELTA.a wider than the other region of a width .DELTA.W formed around its contact portion 45-1 or 45-2 contacting a corresponding second-level metal wiring layer. Accordingly, a distance .DELTA.d1 between the wider regions (located around the contact portions) of the adjacent layers 43-1 and 43-2 is narrower by 2.DELTA.a than a distance .DELTA.d2 between the other regions. Further, the distance between the axes of the adjacent layers 43-1 and 43-2 is ".DELTA.W+.DELTA.d2".
In this case, if the distance .DELTA.d1 between the wider regions of each adjacent pair of first-level metal wiring layers is kept at a minimum pitch, i.e., at a minimum distance determined by the design rule, the distance .DELTA.d2 between the other regions is larger by 2.DELTA.a than the minimum pitch .DELTA.d1. This means that high densification of the first-level metal wiring layers 43 is limited by the allowance value .DELTA.a. Although the width .DELTA.W of the first-level metal wiring layer 43 has been reduced in accordance with development of a technique for refining semiconductor elements, the allowance value .DELTA.a cannot greatly be reduced. Thus, the ratio of the allowance .DELTA.a to the wiring pitch .DELTA.d1 has been increased, and has become a factor in the prevention of high integration of a semiconductor device.